Low profile ball grid array package

ABSTRACT

The present invention is a method and apparatus for a very low profile ball grid array package. A substrate is provided with an aperture. A thin sheet material is secured to the substrate, covering the aperture, so as to form a cavity. A semiconductor die is mounted in the formed cavity on the thin sheet material. The semiconductor die is encapsulated with the thin sheet material supporting it during encapsulation. The use of the thin sheet material to form the cavity is a cost effective way to construct a ball grid array package having a very low profile.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor package and moreparticularly to a low cost cavity type ball grid array (BGA)semiconductor package with a very low profile and to a method for itsfabrication.

BACKGROUND OF THE INVENTION

[0002] Semiconductor devices are widely used in various types ofelectronic products, consumer products, printed circuit cards, and thelike. In an integrated circuit, a number of active semiconductor devicesare formed on a chip of silicon and interconnected in place by leads toform a complete circuit. The size and cost of the semiconductor devicesare important features in many of these applications. Any reduction inthe cost of producing the package or reduction in the size or thicknessof the package can provide a significant commercial advantage.

[0003] Ball grid array semiconductor packages are well known in theelectronics industry. Currently available prior types include thePlastic Ball Grid Array (PGBA), the Ceramic Ball Grid Array (CBGA), andthe Tape Ball Grid Array (TBGA). A BGA package typically comprises asubstrate, such as a printed circuit board, with a series of metaltraces on the top side. This series of metal traces is connected to asecond series of metal traces on the bottom side of the substratethrough a series of wire channels located around the periphery of thesubstrate. A semiconductor die, having a plurality of bond pads, eachassociated with an input or output of the semiconductor die, is mountedto the top side of the substrate. The bond pads are connected to theseries of metal traces on the top side of the substrate by wire bonds.Typically, the semiconductor die and wire bonds are encapsulated with amolding compound. The second series of metal traces located on thebottom side of the substrate each terminate with a contact pad where aconductive solder ball is attached. The conductive solder balls arearranged in an array pattern, and are connected to the next levelassembly or a printed wiring board in the final application.

[0004] Alternatively, the substrate may be provided with a series ofmetal traces on only the bottom side, and the semiconductor die isattached to the bottom of the substrate. The bond pads of thesemiconductor die are attached to the series of metal traces on thebottom side of the substrate. The series of metal traces located on thebottom side of the substrate terminate with a contact pad where aconductive solder ball is attached. The conductive solder balls arearranged in an array pattern, and are connected to the next levelassembly or a printed wiring board in the final application.

[0005]FIG. 1A illustrates a cross-sectional view of a typical prior artperimeter BGA integrated circuit package 10. BGA package 10 comprises asubstrate 11 having top conductive traces 12 formed on an upper surfaceof substrate 11. Substrate 11 typically is formed from an organicepoxy-glass resin based material, such as bismaleimide-triazin (BT)resin or FR-4 board. The thickness of substrate 11 is generally on theorder of 0.35 mm. Bottom conductive traces 13 are formed on a lowersurface of substrate 11 and are electrically connected to top conductivetraces 12 through vias or plated through-holes 14. Vias 14 extend fromthe upper surface of substrate 11 to the lower surface. Vias 14 containa conductive material such as copper. Top conductive traces 12 terminatewith bond posts or pads 21. Bottom conductive traces 13 terminate withball or terminal pads 16. Top conductive traces 12, bottom conductivetraces 13, ball pads 16, and bond posts 21 comprise an electricallyconductive material such as copper or copper plated with gold. Not alltop conductive traces 12, bottom conductive traces 13, and vias 14 areshown to avoid overcrowding of the drawing.

[0006] BGA package 10 further comprises a semiconductor element orsemiconductor die 18 attached to a die attach pad 23 on the uppersurface of substrate 11. Semiconductor die 18 is attached to die attachpad 23 using an epoxy. Semiconductor die 18 has a plurality of bondingor bond pads 22 formed on an upper surface. Each of the plurality ofbond pads 22 is electrically connected to top conductive traces 12 witha wire bond 19. Typically, semiconductor die 18, wire bonds 19, and aportion of substrate 11 are covered by an encapsulating enclosure 24,such as an epoxy enclosure.

[0007] Conductive solder balls 26 are each attached to a ball pad 16.Conductive solder balls 26 are metallurgically wetted to ball pads 16during a reflow process. The inner-most conductive solder balls 26 aretypically underneath or adjacent to semiconductor die 18. Conductivesolder balls 26 are later connected to a next level of assembly orprinted circuit board 28 using a standard reflow process. Conductivesolder balls 26 connect to contact pads 29 to form solder joints 25.After the mounting process, solder joints 25 take a flattened sphericalshape defined by solder volume and wetting areas. The number andarrangement of conductive solder balls 26 on the lower surface ofsubstrate 11 depends on circuit requirements including input/output(I/O), power and ground connections.

[0008]FIG. 1B illustrates a cross-sectional view of another typicalprior art perimeter BGA integrated circuit package 30. BGA package 30comprises a substrate 31 and a support or base substrate 32 attached tosubstrate 31. Substrate 31 and support substrate 32 typically are formedfrom an organic epoxy-glass resin based material, such asbismaleimide-triazin (BT) resin or FR-4 board. The thickness ofsubstrate 31 and support substrate 32 is generally on the order of 0.35mm each. Substrate 31 has an opening or aperture 33, which forms acavity with support substrate 32 as the lower cavity surface. Thedimensions (length and width) of support substrate 32 are greater thanthe dimensions of opening 33 and less than the dimensions of substrate31. Substrate 31 has top conductive traces 34 formed on the uppersurface, and bottom conductive traces 35 formed on the lower surfaceelectrically connected to top conductive traces 34 through vias orplated through holes 36. Top conductive traces 34 terminate at one endwith a bond post or pad 38. Bottom conductive traces 35 terminate with aconductive ball pad or contact 39. A plurality of conductive solderballs or contacts 40 are each coupled to a conductive ball pad 39.

[0009] BGA package 30 also contains a semiconductor element orsemiconductor die 48 attached to a die attach pad 43 on the uppersurface of support substrate 32. Support substrate 32 and opening 33provide a cavity for semiconductor die 48, which minimizes the effect ofdie thickness on the overall package height. Bond pads 42 areelectrically connected to top conductive traces 34 with a wire bond 49.Typically, semiconductor die 48, wire bonds 49 and a portion ofsubstrate 31 are covered by an encapsulating enclosure 50, such as anepoxy enclosure. Conductive solder balls 40 are later connected to anext level of assembly or a printed circuit board 52 using a standardreflow process.

[0010] BGA packages 10, 30 have several disadvantages, including a highprofile. Height 17 of BGA package 10 is typically on the order of 2.4mm, while height 54 of BGA package 30 is typically on the order of 0.9to 1.46 mm. It is often desirable to minimize the thickness of apackaged semiconductor device since they are widely used in varioustypes of electronic products, portable consumer products, telephones,pagers, automobiles, integrated circuit cards, and the like, in order tomake the final products as thin as possible. Thus, there exists a needin the electronics industry for a BGA package that has a very lowprofile.

[0011] Another disadvantage of BGA packages 10, 30 is the cost ofproduction. The use of substantial amounts of substrate in themanufacturing of BGA packages increases the overall cost of production.Thus, there exists a need in the electronics industry for a BGA packagethat is cost effective.

[0012] The present invention has been designed to address the needs ofthe electronics industry and to overcome some of the limitationsassociated with a low cost, low profile BGA package.

SUMMARY OF THE INVENTION

[0013] The present invention advantageously provides a low costsemiconductor device having a very low profile on the order ofapproximately 0.7 mm, and a method for making the same.

[0014] In one embodiment, a single or multi-layered substrate, havingconductive traces on at least the top and bottom sides, is provided withan opening. A layer of very thin material, such as polyimide or metalfoil based tape, is secured on the bottom side of the substrate to coverthe opening in the substrate. A semiconductor die is inserted into thecavity formed by the opening in the substrate and the tape. Thesemiconductor die has a plurality of input/output terminals on its topsurface, which are electrically connected to the conductive traces onthe top of the substrate by bonding wires. The top conductive traces ofthe laminate are connected to the bottom conductive traces of thesubstrate by vias. Contacts or solder balls are connected to the bottomconductive traces of the substrate for connection to a next level ofassembly or a printed wiring board. The semiconductor die, bond wiresand part of the substrate are typically encapsulated with anencapsulating material.

[0015] In a second embodiment, a single or multi-layered substratehaving conductive traces on at least the bottom side is provided with anopening. A layer of very thin material, such as polyimide or metal foilbased tape, is secured to the top side of the substrate to cover theopening. A semiconductor die is mounted upside down in the downwardfacing cavity formed by the opening in the substrate and tape. Thesemiconductor die has a plurality of input/output terminals on its topsurface, which is now facing downward, which are electrically connectedto the conductive traces on the bottom of the substrate by wire bonds.Contacts or solder balls are connected to the bottom conductive tracesof the substrate for connection to a next level of assembly or a printedwiring board. The semiconductor die; bond wires and part of thesubstrate are typically encapsulated with an encapsulating material.

[0016] Thus, in one aspect the invention provides a semiconductor devicewhich has a very low profile on the order of 0.7 mm.

[0017] In yet another aspect the invention provides a semiconductordevice with a very low profile which can be manufactured at a very lowcost.

[0018] In yet another aspect the invention provides a method formanufacturing a low cost, very low profile semiconductor device.

[0019] The above and other objects, advantages, and features of theinvention will become more readily apparent from the following detaileddescription of the invention which is provided in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIGS. 1A and 1B illustrate diagrammatic cross-sectional views ofprior art perimeter BGA packages;

[0021]FIG. 2 illustrates a diagrammatic cross-sectional view of a ballgrid array package according to the present invention;

[0022]FIG. 3 illustrates a diagrammatic cross-sectional view of analternate ball grid array package according to the present invention;

[0023]FIG. 4 illustrates a top view of an integrated circuit containingmultiple ball grid array packages according to the present invention;and

[0024]FIG. 5 is a block diagram of a typical processor controlled systemin which the present invention would be used.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0025] The present invention will be described as set forth in thepreferred embodiments illustrated in FIGS. 2-5. Other embodiments may beutilized and structural or logical changes may be made without departingfrom the scope of the present invention.

[0026] A ball grid array (BGA) package according to the presentinvention is illustrated generally at 100 in FIG. 2 in diagram form. BGApackage 100 comprises a substrate 102 having top conductive traces 104formed on an upper surface of substrate 102. Substrate 102 can be ofeither a single or multi-layered construction as is commonly known inthe art, and typically is formed from an organic epoxy-glass resin basedmaterial, such as bismaleimide-triazin (BT) resin or FR-4 board as iscommonly known in the art. The thickness of substrate 102 is typicallyon the order of 0.35 mm. Bottom conductive traces 106 are formed on alower surface of substrate 102 and are electrically connected to topconductive traces 104 through vias or plated through-holes 108. Vias 108contain a conductive material such as copper. Top conductive traces 104terminate with bond posts or pads 110. Bottom conductive traces 106terminate with ball or terminal pads 112. Top conductive traces 104,bottom conductive traces 106, ball pads 112, and bond posts 110 comprisean electrically conductive material such as copper or copper plated withgold, as is known in the art. Not all top conductive traces 104, bottomconductive traces 106, and vias 108 are shown.

[0027] Substrate 102 has an opening or aperture 114, extending from thetop surface of substrate 102 to the bottom surface of substrate 102. Anupward facing cavity is formed by securing a support base such as thinsheet material 116 to the bottom of substrate 102 to cover aperture 114.Thin sheet material 116 is typically any type of polyimide or metal foilbased or backed material, such as copper or aluminum, on the order ofapproximately 0.025 to 0.01 mm thick and preferably 0.05 mm thick, andmust be able to withstand temperatures involved in typical solder reflowprocesses without degradation. An adhesive may be used to secure thethin sheet material 116 to substrate 102. The adhesive could be athermoplastic, thermoset, or pressure sensitive type. The dimensions(length and width) of the thin sheet material 116 are greater than thedimensions (length and width) of aperture 114 so as to completely coveraperture 114, but typically less than the dimensions (length and width)of substrate 102.

[0028] BGA package 100 further comprises a semiconductor element or die120 mounted in the cavity formed by the aperture 114 and thin sheetmaterial 116, which minimizes the effect of die thickness on the overallpackage height. Semiconductor element 120 has a plurality of bondingpads 122 formed on an upper surface. Each of the plurality of bond pads122 is electrically connected to top conductive traces 104 with a wirebond 124. Typically, a solder mask material (not shown) with openingsover the bond posts 110 and ball pads 112 is applied to the outersurfaces of the substrate 102. Typically, semiconductor element 120,wire bonds 124, and a portion of substrate 102 are covered by anencapsulating compound 126, such as epoxy.

[0029] Conductive solder balls 128 are each attached to a ball pad 112.Conductive solder balls 128 are later connected to a next level ofassembly or printed circuit board 302 (FIG. 4) using a standard reflowprocess. The number and arrangement of conductive solder balls 128 onthe lower surface of substrate 102 depends on circuit requirementsincluding input/output, power and ground connections.

[0030]FIG. 3 illustrates a portion of a cross-sectional view of afurther embodiment of a BGA package 200 according to the presentinvention. BGA package 200 comprises a substrate 202 having bottomconductive traces 204 formed on a lower surface of substrate 202.Substrate 202 can be of either a single or multi-layered construction asis commonly known in the art, and typically is formed from an organicepoxy-glass resin based material, such as bismaleimide-triazin (BT)resin or FR-4 board as is commonly known in the art. The thickness ofsubstrate 202 is typically on the order of 0.35 mm. Bottom conductivetraces 204 terminate with ball or terminal pads 212. Bottom conductivetraces 204 and ball pads 212 comprise an electrically conductivematerial such as copper or copper plated with gold, as is known in theart. Not all bottom conductive traces 204 are shown.

[0031] Substrate 202 has an opening or aperture 214 extending from thetop surface of substrate 202 to the bottom surface of substrate 202. Adownward facing cavity is formed by securing a support material such asthin sheet material 216 to the top surface of substrate 202 to coveraperture 214. Thin sheet material 216 is typically any type of polyimideor metal foil based or backed material, such as copper or aluminum, onthe order of approximately 0.025 to 0.01 mm thick and preferably 0.05 mmthick, and must be able to withstand temperatures involved in typicalsolder reflow processes without degradation. An adhesive may be used tosecure the thin sheet material 216 to substrate 202. The adhesive couldbe a thermoplastic, thermoset, or pressure sensitive type. Thedimensions (length and width) of the thin sheet material 216 are greaterthan the dimensions (length and width) of aperture 214 so as tocompletely cover aperture 214, but typically less than the dimensions(length and width) of substrate 202.

[0032] BGA package 200 further comprises a semiconductor element or die220 inverted and mounted in the cavity formed by the aperture 214 andthin sheet material 216, which minimizes the effect of die thickness onthe overall package height. Semiconductor element 220 has a plurality ofbonding pads 222 formed on its upper surface, which is now facingdownwards. Each of the plurality of bond pads 222 is electricallyconnected to bottom conductive traces 204 with a wire bond 224.Typically, a solder mask material (not shown) with openings over thebond pads 222 and ball pads 212 is applied to the outer surfaces of thesubstrate 202. Typically, semiconductor element 220, wire bonds 224, anda portion of substrate 202 are covered by an encapsulating compound 226.

[0033] Conductive solder balls 228 are each attached to a ball pad 212.Conductive solder balls 228 are later connected to a next level ofassembly or printed circuit board 302 (FIG. 4) using a standard reflowprocess. The number and arrangement of conductive solder balls 228 onthe lower surface of substrate 202 depends on circuit requirementsincluding input/output, power and ground connections.

[0034]FIG. 4 illustrates an integrated circuit 300, such as a SDRAM orSLDRAM memory module or the like, which utilizes multiple ball gridarray packages according to the present invention. Integrated circuit300 is comprised of printed circuit board 302. Printed circuit board 302contains a plurality of top conductive traces 304 on the top surface,and may or may not contain conductive traces on the bottom surface orintermediate layers. Mounted on printed circuit board 302 are variouselectronic components 304, as necessary for operation of the integratedcircuit 300, and low profile ball grid array packages 308 ashereinbefore described with reference to FIGS. 2 and 3.

[0035] Printed wiring board 302 is provided with input/output connectors310 for connection in an end product system (FIG. 5). The use of the lowprofile ball grid array packages 308 minimizes the overall height of theintegrated circuit 300 and allows for smaller end-product packaging.

[0036] A typical processor system which includes integrated circuits,such as memory devices, that contain low profile ball grid arraypackages according to the present invention, is illustrated generally at400 in FIG. 5 in block diagram form. A computer system is exemplary of adevice having integrated circuits such as memory devices. Mostconventional computers include memory devices permitting the storage ofsignificant amounts of data. The data is accessed during operation ofthe computers. Other types of dedicated processing systems, e.g. radiosystems, television systems, GPS receiver systems, telephones andtelephone systems also contain integrated circuit devices which canutilize the present invention.

[0037] A processor system, such as a computer system, generallycomprises a memory device 402, such as a SDRAM or SLDRAM memory module,a memory device controller 403, a central processing unit (CPU) 404,input devices 406, display devices 408, and/or peripheral devices 410.It should be noted that a system may or may not include some or all ofthe aforementioned devices, and may or may not include multiple devicesof the same type.

[0038] Memory device 402 and CPU 404 include integrated circuits whichcontain ball grid array packages according to the present inventionhereinbefore described with reference to FIGS. 2 and 3. The use of lowprofile ball grid array packages according to the present inventionreduces the size and cost of the integrated circuits, effectivelyreducing the size and cost of the end product processor system.

[0039] Reference has been made to preferred embodiments in describingthe invention. However, additions, deletions, substitutions, or othermodifications which would fall within the scope of the invention definedin the claims may be found by those skilled in the art and familiar withthe disclosure of the invention. Any modifications coming within thespirit and scope of the following claims are to be considered part ofthe present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A low profile ball grid array semiconductorpackage comprising: a base substrate having a top surface and a bottomsurface, with an aperture therein which extends from said top surface tosaid bottom surface; a thin sheet material secured to said basesubstrate and covering said aperture such that a cavity is formed; and asemiconductor element mounted in said cavity.
 2. The low profile ballgrid array semiconductor package according to claim 1, said thin sheetmaterial further comprising: a polyimide based material having athickness of approximately 0.025 to 0.1 mm.
 3. The low profile ball gridarray semiconductor package according to claim 1, said thin sheetmaterial further comprising: a metal foil based material having athickness of approximately 0.025 to 0.1 mm.
 4. The low profile ball gridarray semiconductor package according to claim 1 further comprising: anencapsulant covering at least a portion of said semiconductor elementand said base substrate.
 5. A low profile ball grid array semiconductorpackage comprising: a base substrate having a top surface and a bottomsurface, said base substrate having an aperture extending from said topsurface to said bottom surface; a series of conductive traces located onsaid bottom surface of said base substrate; a plurality of conductiveballs connected to said series of conductive traces; a thin sheetmaterial thick secured to said top surface of said base substrate andcovering said aperture to form a downward facing cavity; and asemiconductor element mounted in said downward facing cavity.
 6. The lowprofile ball grid array semiconductor package according to claim 5,wherein said thin sheet material has a thickness in the range ofapproximately 0.025 to 0.1 mm.
 7. The low profile ball grid arraysemiconductor package of claim 6, said thin sheet material furthercomprising: a polyimide based material.
 8. The low profile ball gridarray package of claim 6, said thin sheet material further comprising: ametal foil based material.
 9. The low profile ball grid array package ofclaim 5 further comprising: an encapsulant covering at least a portionof said semiconductor element and said base substrate.
 10. A low profileball grid array semiconductor package comprising: an insulatingsubstrate having a top surface and a bottom surface, said insulatingsubstrate having an aperture extending from said top surface to saidbottom surface; a first series of conductive traces located on said topsurface of said insulating substrate and a second series of conductivetraces located on said bottom surface of said insulating substrate, saidfirst series connected to said second series by via holes in saidinsulating substrate; a thin sheet material approximately 0.025 to 0.1mm thick secured to said bottom surface of said insulating substrate andcovering said aperture such that a cavity is formed; a semiconductorelement mounted in said cavity, said semiconductor element having aplurality of bond pads, each of said bond pads associated with an inputor an output of said semiconductor element; a plurality of wire bondsconnecting said bond pads of said semiconductor element to said firstseries of conductive traces; a plurality of conductive balls connectedto said second series of conductive traces; and an encapsulant coveringat least a portion of said semiconductor element and said insulatingsubstrate.
 11. The low profile ball grid array semiconductor package ofclaim 10, said thin sheet material further comprising: a polyimide basedmaterial.
 12. The low profile ball grid array package of claim 10, saidthin sheet material further comprising: a metal foil based material. 13.A low profile ball grid array semiconductor package comprising: aninsulating substrate having a top surface and a bottom surface, saidinsulating substrate having an aperture extending from said top surfaceto said bottom surface; a series of conductive traces located on saidbottom surface of said insulating substrate; a thin sheet material thicksecured to said top surface of said insulating substrate and coveringsaid aperture such that a downward facing cavity is formed; asemiconductor element mounted in said downward facing cavity, saidsemiconductor element having a plurality of bond pads, each of said bondpads associated with an input or an output of said semiconductorelement; a plurality of wire bonds connecting said bond pads of saidsemiconductor element to said series of conductive traces; a pluralityof conductive balls connected to said series of conductive traces; andan encapsulant covering at least a portion of said semiconductor elementand said insulating substrate.
 14. The low profile ball grid arraysemiconductor package according to claim 13, wherein said thin sheetmaterial has a thickness in the range of approximately 0.025 to 0.1 mm.15. The low profile ball grid array semiconductor package of claim 14,said thin sheet material further comprising: a polyimide based material.16. The low profile ball grid array package of claim 14, said thin sheetmaterial further comprising: a metal foil based material.
 17. Anintegrated circuit comprising: a plurality of low profile ball gridarray semiconductor packages; and a plurality of leads connecting saidplurality of ball grid array semiconductor packages together to form acomplete circuit, said low profile ball grid array semiconductorpackages further comprising a semiconductor element mounted in a cavityon a thin sheet material approximately 0.025 to 0.1 mm thick.
 18. Theintegrated circuit of claim 17, each of said low profile ball grid arraysemiconductor packages further comprising: a base substrate having a topsurface and a bottom surface, said base substrate having an apertureextending from said top surface to said bottom surface, said thin sheetmaterial being secured to said bottom surface of said base substrate tocover said aperture and form said cavity, said semiconductor elementbeing mounted in said cavity on said thin sheet material; a first seriesof conductive traces located on said top surface of said base substrateand a second series of conductive traces located on said bottom surfaceof said base substrate, said first series of conductive traces beingconnected to said second series of conductive traces by via holes insaid base substrate; a plurality of bond pads on said semiconductorelement, each of said bond pads associated with an input or output ofsaid semiconductor element; a plurality of wire bonds connecting saidbond pads of said semiconductor element to said first series ofconductive traces; a plurality of conductive balls connected to saidsecond series of conductive traces; and an encapsulant covering at leasta portion of said semiconductor element and said base substrate.
 19. Theintegrated circuit of claim 17, each of said low profile ball grid arraypackage further comprising: a base substrate having a top surface and abottom surface, said base substrate having an aperture extending fromsaid top surface to said bottom surface, said thin sheet material beingsecured to said top surface of said base substrate to cover saidaperture and form said cavity in a downward direction, saidsemiconductor element being mounted in said downward cavity; a series ofconductive traces located on said bottom surface of said base substrate;a plurality of bond pads on said semiconductor element, each of saidbond pads associated with an input or output of said semiconductorelement; a plurality of wire bonds connecting said bond pads of saidsemiconductor element to said series of conductive traces; a pluralityof conductive balls connected to said series of conductive traces; andan encapsulant covering at least a portion of said semiconductor elementand said base substrate.
 20. A device for mounting a semiconductorelement comprising: an insulating substrate, said insulating substratehaving a top surface and a bottom surface, with an aperture thereinextending from said top surface to said bottom surface; and a thin sheetmaterial approximately 0.025 to 0.1 mm thick secured to said bottomsurface of said insulating substrate and covering said aperture to forman upwards facing cavity, wherein said semiconductor element is mountedin said cavity.
 21. The device for mounting a semiconductor elementaccording to claim 20, said thin sheet material further comprising: apolyimide based material.
 22. The device for mounting a semiconductorelement according to claim 20, said thin sheet material furthercomprising: a metal foil based material.
 23. A device for mounting asemiconductor element comprising: an insulating substrate, saidinsulating substrate having a top surface and a bottom surface, with anaperture therein extending from said top surface to said bottom surface;and a thin sheet material approximately 0.025 to 0.1 mm thick secured tosaid top surface of said insulating substrate and covering said apertureto form a downwards facing cavity, wherein said semiconductor element ismounted in said downwards facing cavity.
 24. The device for mounting asemiconductor element according to claim 23, said thin sheet materialfurther comprising: a polyimide based material.
 25. The device formounting a semiconductor element according to claim 23, said thin sheetmaterial further comprising: a metal foil based material.
 26. A printedcircuit board comprising: a plurality of low profile ball grid arraysemiconductor packages; and a plurality of leads connecting saidplurality of ball grid array semiconductor packages together to form acomplete circuit, said low profile ball grid array semiconductorpackages further comprising a semiconductor element mounted in a cavityon a thin sheet material.
 27. The printed circuit board according toclaim 26, wherein said thin sheet material has a thickness in the rangeof approximately 0.025 to 0.1 mm.
 28. The printed circuit boardaccording to claim 27, each of said low profile ball grid arraysemiconductor packages further comprising: a base substrate having a topsurface and a bottom surface, said base substrate having an apertureextending from said top surface to said bottom surface, said thin sheetmaterial being secured to said bottom surface of said base substrate tocover said aperture and form said cavity, said semiconductor elementbeing mounted in said cavity on said thin sheet material; a first seriesof conductive traces located on said top surface of said base substrateand a second series of conductive traces located on said bottom surfaceof said base substrate, said first series of conductive traces beingconnected to said second series of conductive traces by via holes insaid base substrate; a plurality of bond pads on said semiconductorelement, each of said bond pads associated with an input or output ofsaid semiconductor element; a plurality of wire bonds connecting saidbond pads of said semiconductor element to said first series ofconductive traces; a plurality of conductive balls connected to saidsecond series of conductive traces; and an encapsulant covering at leasta portion of said semiconductor element and said base substrate.
 29. Theprinted circuit board according to claim 27, each of said low profileball grid array semiconductor packages further comprising: a basesubstrate having a top surface and a bottom surface, said base substratehaving an aperture extending from said top surface to said bottomsurface, said thin sheet material being secured to said top surface ofsaid base substrate to cover said aperture and form said cavity in adownward direction, said semiconductor element being mounted in saidcavity; a series of conductive traces located on said bottom surface ofsaid base substrate; a plurality of bond pads on said semiconductorelement, each of said bond pads associated with an input or output ofsaid semiconductor element; a plurality of wire bonds connecting saidbond pads of said semiconductor element to said series of conductivetraces; a plurality of conductive balls connected to said series ofconductive traces; and an encapsulant covering at least a portion ofsaid semiconductor element and said base substrate.
 30. A method forfabricating a low profile ball grid array semiconductor packagecomprising the steps of: providing a base substrate, said base substratehaving a top surface and a bottom surface, with an aperture extendingfrom said top surface to said bottom surface; forming a cavity with saidaperture and a thin sheet material; and mounting a semiconductor elementin said cavity.
 31. The method for fabricating a low profile ball gridarray semiconductor package according to claim 30, wherein said thinsheet material has a thickness in the range of approximately 0.025 to0.1 mm.
 32. The method for fabricating a low profile ball grid arraysemiconductor package according to claim 31, said step of forming acavity further comprising: securing said thin sheet material to saidbottom surface of said base substrate to cover said aperture to form anupward facing cavity.
 33. The method for fabricating a low profile ballgrid array semiconductor package according to claim 31, said step offorming a cavity further comprising: securing said thin sheet materialto said top surface of said base substrate to cover said aperture toform a downward facing cavity.
 34. The method for fabricating a lowprofile ball grid array semiconductor package according to claim 31further comprising the step of: encapsulating at least a portion of saidsemiconductor element and said base substrate.
 35. A method for mountinga semiconductor die comprising the steps of: providing a base substratehaving a top surface and a bottom surface with an aperture extendingfrom said top surface to said bottom surface; forming a cavity bysecuring a support material approximately 0.025 to 0.1 mm thick to saidbase substrate to cover said aperture; and mounting said semiconductordie in said cavity.
 36. The method for mounting a semiconductor dieaccording to claim 35, said step of forming a cavity further comprising:securing said support material to said bottom surface of said basesubstrate to form an upwards facing cavity.
 37. The method for mountinga semiconductor die according to claim 35, said step of forming a cavityfurther comprising: securing said support material to said top surfaceof said base substrate to form a downwards facing cavity.
 38. The methodfor mounting a semiconductor device according to claim 35 furthercomprising the step of: encapsulating at least a portion of saidsemiconductor die and said base substrate.
 39. A processor systemcomprising: a central processing unit; and a memory device connected tosaid central processing unit, said memory device comprised of aplurality of ball grid array semiconductor packages, said ball gridarray semiconductor packages comprised of an insulating substrate havinga top surface and a bottom surface, said insulating substrate having anaperture therein extending from said top surface to said bottom surface,a thin sheet material approximately 0.025 to 0.1 mm thick secured tosaid top side of said substrate to form a cavity, and a semiconductordie mounted in said cavity.
 40. The processor system according to claim39, said thin sheet material further comprising: a polyimide basedmaterial.
 41. The processor system according to claim 39, said thinsheet material further comprising: a metal foil based material.
 42. Aprocessor system comprising: a central processing unit; and a memorydevice connected to said central processing unit, said memory devicecomprised of a plurality of ball grid array semiconductor packages, saidball grid array semiconductor packages comprised of an insulatingsubstrate having a top surface and a bottom surface, said insulatingsubstrate having an aperture therein extending from said top surface tosaid bottom surface, a thin sheet material approximately 0.025 to 0.1 mmthick secured to said bottom side of said substrate to form a cavity,and a semiconductor die mounted in said cavity.
 43. The processor systemaccording to claim 42, said thin sheet material further comprising: apolyimide based material.
 44. The processor system according to claim42, said thin sheet material further comprising: a metal foil basedmaterial.